Formation of junctions and silicides with reduced thermal budget

ABSTRACT

Method of formation of a metal-silicide layer ( 12, 13, 14, 18, 19 ) an a semiconductor substrate ( 1 ), the semiconductor substrate ( 1 ) including at least a dopant region ( 5 ); the dopant region ( 5 ) including an ultra-shallow junction region; the method including as a first step at least one impurity implantation process (IB dopant) for forming the dopant region ( 5 ); the method including as a second step at least one metal implantation process (IB metal) for forming the metal-silicide layer ( 12, 13, 18, 19 ) an the dopant region ( 5 ), and the method including, as a third step carried out after the first and the second step, a low-temperature annealing process wherein simultaneously the dopant region ( 5 ) is activated and the metal-silicide layer ( 12, 13, 14, 18, 19 ) is formed.

The present invention relates to a method of manufacturing asemiconductor device comprising the step of forming a metal silicide foruse in micro-electronic manufacturing applications.

To obtain higher device densities and/or higher operation speeds in manytypes of micro-electronic devices (integrated circuits), the design ofnew generations of such devices shows a tendency to use structuralelements such as MOSFET transistors which occupy a smaller part of achip area and also have a shallower depth than in previous devicegenerations.

In newer device generations, the junctions in a MOSFET are reduced to arelatively shallow depth. Typically, in a first metallization level thejunctions, i.e. source and drain regions, are provided with a conductinglayer on top of them for electrical connections. Preferably, metalsilicide is used as metallization since silicidation by a self-alignedformation process allows a relatively simple definition of theconducting elements.

During the formation of the metallization of the junctionssimultaneously the gate conduction region of the MOSFET is covered bythe same conducting metal silicide.

From U.S. Pat. No. 6,294,434 (Tseng) it is known to use an implantationprocess to deposit a suitable metal in the top surface of the junctions,which metal reacts to a metal-silicide in a subsequent annealing processwith silicon in the junction and gate regions (and other siliconcontaining regions) exposed during the implantation process. In a firstanneal, the junction and gate regions obtain a metal-silicide layer.Then, a cleaning process is applied to remove unreacted metal. Finally,a second anneal is applied to reduce the resistance of the metalsilicide.

For IC designs with ultra-shallow junctions, however, in such afabrication process the annealing processes for formation of thesilicide layer may adversely affect the dopant profiles in the junctionregions. The risk of deactivation of junctions due to (excess) thermalexposure may be appreciable and the yield of a manufacturing process forICs of such a design may be affected. Consequently, the process windowsare typically relatively narrow and need to be employed with great careto avoid any negative influence on the devices to be created.

It is an object of the present invention to provide a method ofmanufacturing a semiconductor device comprising the step of forming ametal silicide which does not adversely affect the properties of deviceshaving ultra-shallow junctions.

This object is achieved by a process as defined in the preamble of claim1, characterized in that the method is arranged to carry out after thefirst and the second step: as a third step a low-temperature annealingprocess wherein simultaneously the dopant region is activated and themetal-silicide layer is formed.

In the present invention, the activation of the junction regions and thesilicide regions is performed in a single annealing process by solidphase epitaxial regrowth. Advantageously, simultaneous activation of thejunction regions and formation of silicide will eliminate thedeactivation of the ultra-shallow junction regions due to the thermalbudget involved in additional annealing processes for silicide formationin the prior art.

Also, the single process advantageously reduces the number of processingsteps in the fabrication process of micro-electronic devices withultra-shallow junctions of the type as described above.

Moreover, the present invention provides good control of the silicidepenetration depth due to the relatively low annealing temperature whichcauses the diffusion coefficients to be fairly low.

Furthermore, the present invention provides the possibility of a freeselection of metal for silicide formation, in particular metals whichform a silicide with a high stoichiometric silicon-metal ratio, such asa metal-di-silicide, may be preferred.

Additionally, by selection of a metal for implantation in relation tothe conductivity type of the junction, the method according to thepresent invention provides that the work function can be matched foreach junction in relation to its conductivity type and its respectivedopant level.

Further, the present invention relates to a semiconductor device on asemiconductor substrate comprising a dopant region comprising anultra-shallow junction, wherein the semiconductor device is manufacturedby a method of formation of a metal-silicide layer as described above.

For the purpose of teaching the invention, preferred embodiments of themethod and devices of the invention are described below. It will beappreciated by the person skilled in the art that other alternative andequivalent embodiments of the invention can be conceived and reduced topractice without departing form the true spirit of the invention, thescope of the invention being limited only by the appended claims.

Below, the invention will be explained with reference to some drawings,which are intended for illustration purposes only.

FIG. 1 shows schematically a cross-section of a semiconductor deviceduring a first process in accordance with the method of the presentinvention;

FIG. 2 shows schematically a cross-section of a semiconductor deviceduring a second process according to the present invention;

FIG. 3 shows schematically a cross-section of a semiconductor deviceduring a third process according to the present invention;

FIG. 4 shows schematically a cross-section of a semiconductor deviceafter a fourth process according to the present invention;

FIG. 5 shows schematically a cross-section of a semiconductor device ina further embodiment according to the present invention.

The present invention relates to the fabrication of micro-electronicdevices which comprise ultra-shallow junctions and a silicide layercovering such junctions. FIG. 1 shows schematically a cross-section of asemiconductor device during a first process in accordance with themethod of the present invention.

On a semiconductor substrate 1, such as a monocrystalline silicon waferor a silicon-on-insulator substrate, the regions 2 where a junction willbe formed are prepared in a first process. After definition of a mask 3which delineates the area of the regions 2, a pre-amorphisation processof the regions 2 is performed. The pre-amorphisation process is done byion-beam implantation by an ion beam IB_pre. The ion beam IB_pre isschematically indicated by arrows.

As ion source material Ge, GeF₂ or Si may be used. However, otherelements may also be used such as heavy noble elements Ar, and Xe.

Typical parameters for a pre-amorphisation process are, e.g., for Ge abeam acceleration energy in the range 2-30 keV, with a dose of2×10¹⁴-5×10¹⁵ atoms/cm².

By the ion beam irradiation of the exposed regions 2 the crystallinestructure of the substrate material 1 in those regions 2 is transformedinto an amorphous state.

FIG. 2 shows schematically a cross-section of a semiconductor deviceduring a second process according to the present invention.

In the second process the implantation of the impurities as dopant toform doped regions 4 is carried out. The mask 3′ is used to delineatethe regions 2 where implantation must be carried out. The dopantimplantation process is schematically indicated by arrows IB_dopant.

The impurities which are implanted are chosen to obtain the desiredconductivity type of the doped regions 4. The impurities (e.g., B, As,P, etc.) are implanted at low energy (typically less than 5 keV) and ina dose of approximately 1×10¹⁵ atoms/cm², in accordance with the desiredcharacteristics of the junction to be formed.

FIG. 3 shows schematically a cross-section of a semiconductor deviceduring a third process according to the present invention.

In the third process the silicidation regions are defined where asilicide layer is to be formed. A mask 3″ is formed which delineates theregions to be silicided. These silicidation regions may be regions 5that overlap with doped regions 4, or it may be conduction regions 6covering regions 2 which were only amorphised in the first process andnot exposed in the second process of doped region formation. Suchconduction regions 6 may be located at different locations than thedopant regions 4.

Also, the silicidation region may be a region 9 on top of a gate G. Agate 7 is schematically depicted here as a thin gate oxide layer 10, apoly-Si layer portion 7, and spacers 8. The top of the poly-Si layerportion 7 may have been pre-amorphised in the first processsimultaneously with the junction regions 2, as will be appreciated bypersons skilled in the art.

Next, a metal implantation process is performed for a metal chosen toform a metal-silicide (of a desired composition depending on the actualmetal). Again an ion beam implantation process is carried out asschematically indicated by arrows IB_metal. Typical process parametersfor the low energy process are: a beam energy between about I and about20 keV, and a dose of approximately 1×10¹⁶-5×10¹⁷ atoms/cm². The metalcan be chosen in accordance with the desired properties of the silicide(i.e., resistivity, work function, compatibility with furtherprocessing, etc.). Preferably, a metal may be chosen which may form ametal-silicide with a high Si: metal ratio, such as a metal-di-silicide,which requires a lower metal implant dose and simultaneously may offer alower sheet resistance in comparison to other metal-silicidemodifications of the same metal. The metal may be chosen from Co, Ni,Hf, Ti, Mo, W, or any other metal capable of forming a suitable silicidecompound.

In the present invention, the choice of metal is not limited tometal-silicides which are epitaxial on the semiconductor substrate(e.g., silicon Si(100) or Si(111)).

It is noted that in the present invention the order of the secondprocess of impurity implantation and the third process of metalimplantation may be reversed.

FIG. 4 shows schematically a cross-section of a semiconductor deviceafter a fourth process according to the present invention.

The fourth process encompasses a solid phase epitaxial regrowth (SPER)process. During a low temperature annealing process (e.g., rapid thermalannealing) at a relatively low annealing temperature of approx. 550 toapprox. 750° C. during approx. 1 minute, the doped regions 5, 6 areepitaxially regrown with the same crystal structure as the semiconductorsubstrate layer 1. In the lower parts of the regions 5, activatedjunctions 11 of the conductivity type as defined by the implantedimpurity are formed, in the upper part of the regions 5, 6 (closer tothe surface) a silicide layer 12 a, 12 b, 13 is formed.

The silicide layer on top of a junction 11 may be formed as a silicidelayer 12 a adjacent to the spacers 8 of the gate G or as a remotesilicide layer 12 b in a region remote from the spacers 8. The silicidelayer may also be formed as a single silicide layer 13 in an othersubstrate region 6 outside a junction region 5.

At the same time, silicide layer 14 may be formed in the top layerportion 9 of the gate G.

The definition of silicide layers 12 a, 12 b, 13, 14 is done by the maskused during the implantation step.

Further, an insulation layer 15 is shown in FIG. 4.

The silicide layer 12 a and the remote silicide layer 12 b are shownnext to the gate G, but as will be appreciated by persons skilled in theart, instead of the gate G any other type of structural element such asLOCOS, a floating gate/control gate stack, etc. is also conceivable. Theremote silicide layer 12 b may even be formed in a junction area withoutany further structural element being present.

FIG. 5 shows schematically a cross-section of a semiconductor device ina further embodiment according to the present invention.

In the preceding FIGS. 1-4 the implantation of impurities intopre-defined regions 2 for forming dopant regions 5 and implantation ofmetal to form conducting layers 12 a, 12 b, 13 on dopant regions 5 or onother regions 6, was described for simply one impurity type and onemetal. It is noted that the present invention allows the combination ofmultiple impurity implantation processes and multiple metal implantationprocesses. By multiple impurity implantation processes, dopant regions 5of different conductivity type can be formed by using differentimpurities in the respective impurity implantation processes. Also,dopant regions 5 of equal conductivity type but with different impuritylevels may be formed in this manner. It is only required to applydifferent masking layers in the respective impurity implantationprocesses.

Similarly, a combination of multiple metal implantation processes ispossible on different areas of the semiconductor substrate. Again,appropriate masking should be used to define the respective areas.Moreover, the combination of multiple implantation processes allows toselect a metal-silicide with a required work function for each area onthe semiconductor substrate depending on the state of the respectivearea (e.g., a dopant region 5 of p-type, a dopant region 5 of n-type, agate conduction region 9, or another conduction region 6).

In FIG. 5, an example is shown which comprises a first ultra-shallowjunction 11 of a first conductivity type which is covered by a firstsilicide layer 12 a, and a second ultra-shallow junction 17 of a secondconductivity type, embedded in an insulating region 16 of oppositeconductivity type.

The insulating region 16 may be formed in any way known to personsskilled in the art, including solid-phase epitaxial regrowth. Moreover,such embedded structures can be formed during a single pre-amorphisationstep, multiple doping and single thermal budget corresponding tojunction- and silicide-formation at the same time.

The second ultra-shallow junction 17 is covered by a second silicidelayer 18. Further, a conduction region is shown which comprises a thirdsilicide layer 19. Likewise, a fourth silicide layer may be present on agate G (not shown). Each of the ultra-shallow junctions 11, 17 is formedby an impurity implantation process for the specific conductivity typeas described above. Each of the suicide layers 12, 18, 19 is formed by ametal implantation process for the specific silicide as described above.The activation of the junctions 11, 17 and the formation of the silicidelayers 12, 18, 19 is done simultaneously in the SPER process in thefourth process. Again, a remote silicide layer 12 b and a singlesilicide layer 13 may be formed in these multiple implantationprocesses. The remote suicide layer 12 b and the single silicide layer13 may accordingly comprise multiple different metal silicides, whichare each defined by the respective metal implantation process.

Finally, it is noted that in the case of creating a dopant region 5 withn-type conductivity by means of an ion beam process (IB_dopant) using Asions, the pre-amorphisation process (IB_pre) may be omitted due toself-amorphising properties of the As ion beam. In this case, the ionbeam process for implanting the impurity element acts simultaneously aspre-amorphisation process (IB_pre).

1. Method of manufacturing a semiconductor device comprising the step offorming a metal-silicide layer on a semiconductor substrate, saidsemiconductor substrate comprising at least a dopant region; said dopantregion comprising an ultra-shallow junction region; said methodcomprising as a first step at least one impurity implantation processfor forming said dopant region; said method comprising as a second stepat least one metal implantation process for forming said metal-silicidelayer on said dopant region characterized in that said method isarranged to carry out after said first and said second step: as a thirdstep a low-temperature annealing process wherein simultaneously saiddopant region is activated and said metal-silicide layer is formed. 2.Method according to claim 1, wherein said method comprises apre-amorphisation process by ion beam carried out as an initial processbefore said first step on at least said dopant region and saidconduction region.
 3. Method according to claim 1, wherein said at leastone impurity implantation process comprises a first impurityimplantation process using a first impurity to create a junction regionof a first conductivity type.
 4. Method according to claim 3, whereinsaid at least one impurity implantation process comprises a secondimpurity implantation process using a second impurity to create ajunction region of a second conductivity type.
 5. Method according toclaim 3, wherein said at least one impurity implantation processcomprises a second impurity implantation process using said firstimpurity to create a further junction region of said conductivity typewith a different impurity level.
 6. Method according to claim 3, whereinsaid at least one metal implantation process for forming saidmetal-silicide layer comprises a first metal implantation process usinga first mask and a first metal to create a first silicide layer on saidjunction region of said first conductivity type.
 7. Method according toclaim 3, wherein said at least one metal implantation process forforming said metal-silicide layer comprises a second metal implantationprocess using a second mask and a second metal to create a secondsilicide layer on said junction region of said second conductivity type.8. Method according to claim 3, wherein said at least one metalimplantation process for forming said metal-silicide layer comprises afurther metal implantation process using a further mask and a furthermetal to create a further silicide layer on said conduction region orsaid gate conduction region.
 9. Method according to claim 1, whereinsaid method comprises in said second step said at least one metalimplantation process for forming said metal-silicide layer on aconduction region.
 10. Method according to claim 1 wherein said methodcomprises in said second step said at least one metal implantationprocess for forming said metal-silicide layer on a gate conductionregion of a gate.
 11. Method according to claim 1, wherein said lowannealing temperature process is a solid-phase epitaxial regrowthprocess.
 12. Method according to claim 1, wherein each of said first,second, or further metal is capable of forming a metal-di-silicidecompound during said low temperature annealing process.
 13. Methodaccording to claim 1, wherein said metal silicide layer is formed as atleast one of a metal silicide layer adjacent to another structuralelement arranged within said junction region, or a remote metal silicidelayer in said junction region remote from said other structural element,and a single metal silicide layer in said conduction region outside ofsaid junction region.
 14. Semiconductor device on semiconductorsubstrate comprising at least a dopant region, said dopant regioncomprising an ultra-shallow junction region, wherein said semiconductordevice is manufactured by a method of formation of a metal-silicidelayer in accordance with claim 1.